Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron CMOS lCs - Test Conference, 1998. Proceedings. International
نویسندگان
چکیده
Transient current testing (IDDT) has been often cited as an alternative and/or supplement to IDDQ testing. In this article we investigate the potential of transient current testing in faulty chip detection with silicon devices. The effectiveness of the IDDT test method is compared with I D D e as well as with SA-based voltage testing. Photon emission microscopy is used to localize defects in several faulty devices. Furthermore, the potential of IDDT testing for leaky deep sub-micron devices is investigated.
منابع مشابه
IDDT Test Methodologies for Very Deep Sub-micron CMOS Circuits
In this paper, we investigate three iDDT-based test methodologies, Double Threshold iDDT, Delta iDDT, and Delayed iDDT, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the th...
متن کاملProbabilistic-based Defect/Fault Characterisation of Complex Gates from Standard Cell Library
The need for development of new approaches for defect/fault analysis of VLSI circuit is growing and becomes even more important as we move further into the sub-micron devices. Yield loss in ICs fabrication and testing of the manufactured ICs now are major bottlenecks in the production of qualitative VLSI circuits. For instance, it is predicted that the test costs for the emerging deep submicron...
متن کاملOxynitride Gate Dielectrics for Deep Sub-micron MOS Devices
The continuous demand for improved CMOS transistors necessitate smailer device dimensions. The reduction in chip size into the deep sub-micron dimensions opens up new scientific and engineering challenges. One of the most critical material in developing deep sub-micron MOS transistors is high quality ultrathin (a few nm) gate dielectric film. As the gate dielectric thickness is reduced to below...
متن کاملAnalysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing
In this work, IDDQ current for the deep sub-micron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ cu...
متن کاملGuest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era
0740-7475/02/$17.00 © 2002 IEEE September–October 2002 CMOS IC SCALING increases device/interconnect density to allow more logic on a die at higher clock rates, enhancing overall performance. Improvements in process technology enable integration on a single die of circuits with different functions that require distinct manufacturing process steps. With added constraints of reduced time to marke...
متن کامل